Charged Device Model (CDM) ESD in ICs
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Author
Date
2006Type
- Doctoral Thesis
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yes
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Abstract
As a result of technology scaling and the broadening of automated handling in production, failures in TCs caused by Charged Device Model (CDM) Electrostatic Discharge (ESD) are an increasingly important reliability issue. Today, a significant portion of ESD field returns are due to damages originating from CDM stress. To be competitive in the fast moving semiconductor industry, companies have to design ICs which meet state-of-the-art requirements for CDM robustnesson the one hand and ensure first Silicon success on the other. Computer Aided Design (CAD) modeis and tools support in fulfilling these requirements. The goal of this thesis is to provide comprehensive information for coping with the challenges of accurate CDM circuit Simulation. In case of a CDM event, the charge carriers which are dispersed over the complete IC and package discharge through the path with the lowest impedance. Apart from power bus and protection devices, this path can lead through Substrate and other parasitic physical layers. The relevance of these parasitic elements for CDM circuit Simulation is demonstratedin this thesis. Also, the behavior of ICs during CDM discharges is strongly affected by the package. This is primarily attributable to the package capacitances which form the main charge source for a CDM event. Due to the high frequencies associated with such events, the discharge behavior is also influenced by the inductive, capacitive and resistive parasitics of package and CDM measuring equipment. The high electric fields between the CDM fester pin and the IC pin can result in a discharge are which reduces the rise time and the amplitude of the discharge current. This work introduces approaches for modelingall these elements and demonstrates that accounting for them in the Simulation setup is essential for achieving correct Simulationresults. When pn junctions are biasedwith fast transient current signals, a voltage overshootcan occur across these devices. In forward bias, this effect is known as forward recovery effect. The impactof this effect on the CDM behavior of devices is investigated with measurements and device Simulation. Compact modeisthat reflect this transient turn-on behavior effectivcly are presented. In reverse bias, an increase of the breakdown voltage of reversed biased pn junctionscan be observed for trigger pulses with voltage slopes in the CDMtime domain. The physical mechanism causing the delayed breakdown is investigated. The relevance of this effect for the behavior of ICs during CDM discharges is discussed. A newly developed automated method for extracting transient, high-current model parameters for circuit Simulation of CDM ESD events is presented. The procedure is performed with transient Signals obtained from very-fast TLP (TransmissionLine Pulse) measurements. This method utilizes the maximum achievable aecuraey of the currently available characterization methods, which reach their limits in the CDM time and current domain. Hence, the proposed method is suitable for determining parameters of compact models that include CDM specific device physical effects. The applicability of the proposed CDM Simulation method for predicting the CDM behavior of ICs correctly is evaluatedwith two case studies in different smart power process generations. First, a CDM specific failure mechanism was investigated for an input protection strueture in a 0.8 u-in technology. CDM tests revealed unexpected dependency of the CDM robustness on design variations. This work demonstrates that the complex, CDM specific failure mechanism can be reproduced accurately with circuit Simulation. Comparison with device Simulation and measurement results showed that even the failure levels can be determined correctly with circuit Simulation. Secondly, the capability of proposed Simulation method to predict the CDM robustness of integrated circuits is verified for variations of an ESD evaluation circuit in a 0.35 um technology. These circuits were designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. Detailed cross-checks are performedbetween CDM tests of different design variations and the corresponding results derived from circuit Simulation. Failure modes and locations which were determined using results from functional measurcments are confirmed with failure analysis. From these results, the conclusioncan be drawn that by employingthe proposed CDM Simulation method, weak circuit elements can be discovered and corrected before Silicon is available. Show more
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https://doi.org/10.3929/ethz-a-005174532Publication status
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ETHSubject
TRANSIENTENANALYSE (ELEKTROTECHNIK); TRANSIENT ANALYSIS (ELECTRICAL ENGINEERING); BESTÜCKUNG VON LEITERPLATTEN (MIKROELEKTRONIK); MIKROELEKTRONIK + INTEGRIERTE SCHALTUNGEN; STATISCHE LADUNG UND ENTLADUNG (ELEKTROSTATIK); STATIC CHARGE AND DISCHARGE (ELECTROSTATICS); MICROELECTRONICS + INTEGRATED CIRCUITS; ASSEMBLY OF PRINTED CIRCUIT BOARDS (MICROELECTRONICS)Organisational unit
03228 - Fichtner, Wolfgang
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