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A 12-core processor implementation on FPGA
| Metadata Label | Value |
|---|---|
| Author(s): | Liu, Ling |
| Publisher: | ETH, Department of Computer Science |
| Citation: | Liu, Ling. A 12-core processor implementation on FPGA. ETH, Department of Computer Science (2009). http://dx.doi.org/10.3929/ethz-a-006819824 |
| Document Type: | Reports |
| Documents: |
Text
(278.57KB) |
Detailed Information
| Metadata | Description |
|---|---|
| Title | A 12-core processor implementation on FPGA |
| Author(s) | Liu, Ling |
| Publication Place | Zurich |
| Publisher | ETH, Department of Computer Science |
| Publication Date | 2009 |
| Series | [Technical report / Swiss Federal Institute of Technology Zurich, Department of Computer Science] [646] |
| Language | English |
| DOI | http://dx.doi.org/10.3929/ethz-a-006819824 |
| Subject(s) | Computer Systems |
| Keyword(s) |
MULTIPLE DATA STREAM ARCHITECTURES PROGRAMMABLE LOGIC DEVICES PLD |
| Organisational Unit | Department of Computer Science |
| Online Publication Date | 2011 |
| Description | File Name | MIME Type | Size |
|---|---|---|---|
| Text |
eth-4974-01.pdf |
application/pdf | 278.57KB |
| Description | URL |
|---|---|
| NEBIS Link | http://opac.nebis.ch/F/?local_base=NEBIS&func=find-b&find_code=SYS&request=006819824 |
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E-Collection record created: Tue, 10 Jan 2012, 06:04:36 CET