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Transistor sizing for timing optimization of combinational digital CMOS circuits
| Metadata Label | Value |
|---|---|
| Author(s): | Heusler, Lucas Sebastian |
| Publisher: | Unknown |
| Citation: | Heusler, Lucas Sebastian. Transistor sizing for timing optimization of combinational digital CMOS circuits. (1990). http://dx.doi.org/10.3929/ethz-a-000578335 |
| Document Type: | Doctoral and Habilitation Theses |
| Documents: |
Abstract
(133.35KB) |
Detailed Information
| Metadata | Description |
|---|---|
| Title | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| Author(s) | Heusler, Lucas Sebastian |
| Publication Place | Zürich |
| Publication Date | 1990 |
| Notes | Diss. Techn. Wiss. ETH Zürich, Nr. 9071, 1990. Ref.: W. Fichtner ; Korref.: W. Guggenbühl |
| Language | English |
| DOI | http://dx.doi.org/10.3929/ethz-a-000578335 |
| Subject(s) | Microelectronics, Integrated Circuits |
| Keyword(s) |
COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS MICROELECTRONICS DIGITAL INTEGRATED CIRCUITS METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUITS METAL OXIDE SEMICONDUCTOR TRANSISTORS ELECTRONICS TRANSISTORS |
| Description | File Name | MIME Type | Size |
|---|---|---|---|
| Abstract |
eth-37992-01.pdf |
application/pdf | 133.35KB |
| Description | URL |
|---|---|
| NEBIS Link | http://opac.nebis.ch/F/?local_base=NEBIS&func=find-b&find_code=SYS&request=000578335 |
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E-Collection record created: Wed, 18 Feb 2009, 12:21:33 CET